Machine Instruction Analysis For Dct Algorithm Using Dlx Architecture

Believa Dyanneley Aritspoundy, Nyoman Bogi Aditya Karna, Raditiana Patmasari

Abstract

To reduce size of images, compressing images are required. This thesis presents a
proof about the advantages using DeLuXe (DLX) microprocessor to do image
compression and ASIP which help to reduce the power of microprocessor to save more
energy for long term using. The simulation using winDLX processor which has to show
the algorithm for Discrete Cosine Transform (DCT) in image compression process, coded
in assembly DLX programming language which is MIPS.
The result of the programs made to simulate DCT using DLX microprocessor
requires total of 14763 cycles executed with total of 5920 instructions. The instructions
which are often used in this experiment is Load Float which is used to load the value of
matrices before being store to the memory and multiplied to other matrices because
mostly the matrices in this simulation consist of decimal numbers.

Keywords: ASIP, Discrete Cosine Transform, DLX microprocessor.

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